1. Field of the Invention
Embodiments of the invention relate to multilayer electronic devices and methods for fabrication of multi-layer electronic devices in which electroplated sacrifical structures are used during fabrication to pattern certain dielectric or other material in one or more layers. Particular embodiments of the invention relate to highly stable multilayer electronic devices and methods of fabrication thereof, for use in caustic or sensitive environments, such as medical and implant environments, in which the material used for a patterned dielectric or other patterned layers in the device are selected, in part, for suitable environmental compatibility.
2. Description of Related Art
A variety of multilayer electronic structures comprised of multiple layers of conductors interposed between multiple layers of dielectric material have been developed for various purposes. For multilayer electronic structures used in caustic or senstitive environments, the materials selected for the dielectric layer or other layers in the multilayer electronic structure preferably not only have suitable electrical characteristics to provide an intended electrical function, but also have suitable characteristics to be compatible with the environment. However, such environmentally compatible materials can, in some contexts, present manufacturing difficulties.
For example, materials traditionally considered compatible (or inert) with respect to certain medical or biological environments may have physical characteristics that render them incapable or impractical to form in layers of suitably precise patterns or suitably large spanses, using traditional multilayer device manufacturing techniques. Materials, such as Al2O3 (alumina) may have suitable dielectric characteristics and may be suitably compatible (or inert) with respect to medical or biological environments. However, traditionally, alumina has been difficult to form in precise patterns.
To address such problems, example processes for patterning alumina by using sacrifical structures formed by shadow masking techniques are described in U.S. patent application Ser. No. 10/671,996, filed 26 Sep. 2003, which is incorporated herein by reference. Shadow masking techniques typically employ machined, laser-drilled masks for defining the pattern of deposition of the patterned layer material. Because of the cost and physical limitations of such masks and laser drilling proceses, shadow masking techniques can be impractical for forming certain pattern shapes or precision details in patterned layers. Also, shadow masking techniques can be impractical for forming patterns in large spanses, such as for large devices or for forming multiple devices simultaneously (such as a multiple-device wafer that is cut into separate devices after formation of the wafer).
Multiple layer circuit devices and processes of making such devices using ceramic substrate materials as described in the above-referenced U.S. patent application Ser. No. 10/671,996 and embodiments included herein are distinguished from silicon-based muli-layer devices in which doped regions of silicon are connected by layers having conductive material. In contrast to silicon based devices, ceramic-based multiple layer circuit devices as described in the above-referenced U.S. patent application Ser. No. 10/671,996 and embodiments included herein may be configured with thick film layers, thin film layers or combinations of thick and thin film layers.
Other multilayer substrates are conventionally fabricated by lamination techniques in which metal conductors are formed on individual dielectric layers, and the dielectric layers are then stacked and bonded together. However, various conventional lamination techniques have limitations that restricts their usefulness. For example, high temperature ceramic co-fire (HTCC) lamination techniques form conductors on “green sheets” of dielectric material that are bonded by firing at temperatures in excess of 1500 degrees C. in a reducing atmosphere. The high firing temperature precludes the use of noble metal conductors such as gold and platinum. As a result, substrates formed by high temperature processing are limited to the use of refractory metal conductors such as tungsten and molybdenum, which have very low resistance to corrosion in the presence of moisture and are therefore not appropriate for use in certain environments.
Low temperature ceramic co-fire (LTCC) techniques also utilize green sheets of ceramic materials. However the dielectric materials used in low-temperature processes are generally provided with a high glass content and therefore have relatively poor resistance to environmental corrosion, as well as a relatively low dielectric constant and relatively poor thermal conductivity.
Thick film (TF) techniques form multilayer substrates by firing individual dielectric layers and then laminating the layers to form a multilayer stack. However, thick film techniques require the use of relatively thick dielectric layers and thus it is difficult to produce a thin film multilayer device or a device having a combination of thick and thin film layers using traditional thick film processing techniques. Thick film dielectrics also have relatively low dielectric constants, relatively poor thermal conductivity, and poor corrosion resistance.
In addition to the problems listed above, the conventional lamination techniques cannot use green sheets of less than 0.006 inches in thickness because thinner green sheets cannot reliably survive necessary processing such as drilling or punching of via holes. Also, because the designer has limited control over the thickness of individual green sheets, the number of layers of the multilayer substrate is often limited according to the maximum allowable substrate thickness for the intended application. Thus, where a thin multilayer substrate device is desired or a multilayer substrate device having both thick and thin layers, lamination techniques generally do not provide optimal results.
In addition, the firing required in the conventional lamination techniques can cause shrinkage in excess of 10% in both dielectric and conductor materials, which can produce distortions that result in misalignment of vias and conductors after firing. While shrinkage effects can be addressed to some extent during design for substrates having a modest interconnect density, the design process is made more time consuming and a significant reduction in yield may occur in applications with higher densities and tighter dimensional tolerances.